In many fields of integrated circuit manufacturing, such as in the manufacture of dynamic random access memories (DRAMs), the circuits have multiple levels of metal or polysilicon above the surface of the silicon substrate. These multiple levels must be interconnected for proper electrical functioning of the circuit, and so it becomes necessary to provide certain types of electrical connections between the various conductive levels and active or passive devices.
For example, when DRAMs are fabricated it is customary to provide word lines at one level within the integrated circuit structure and bit or digit lines at another level. It then becomes necessary to provide vertical interconnects between the word and bit lines and certain devices such as access transistors fabricated within the silicon substrate.
A typical structure is illustrated in U.S. Pat. No. 5,338,700, entitled "Method of Forming A Bit Line Over Capacitor Array of Memory Cells", and assigned to Micron Technology, Inc. First, an n-doped polysilicon plug is self-aligned to the transistor gates and word lines. Then, non-self-aligned tungsten plugs are formed to go down to the n-doped plug, the p-doped active area, and the gate interconnect. The tungsten plugs are not self-aligned; accordingly, without careful alignment it is possible that errors in plug placement may result that short the gates and cause electrical errors in the integrated circuit.
A typical method of forming vertical interconnects with a minimum of masking steps is illustrated in U.S. Pat. No. 5,637,525, entitled "Method of Forming a CMOS Circuitry", and assigned to Micron Technology, Inc.
What is needed is a simpler process for producing low resistance conductive plugs that provide vertical interconnects in a semiconductor structure. Also needed is a process that minimizes deep contacts and improves alignment of etching with respect to the gate with a minimum number of masking and etching steps.